1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to a semiconductor device having a static random access memory (hereinafter referred to as xe2x80x9cSRAMxe2x80x9d) cell.
2. Description of the Prior Art
In recent years, it is important to save energy for and reduce the voltage of a semiconductor device built in a portable device, so that the portable device can be driven by a battery as long as possible. Following this, an SRAM operable at a low voltage with low power consumption is increasingly demanded.
In order to satisfy such requirements, a CMOS memory cell is employed as the memory cell of the SRAM. The CMOS memory cell is formed by four n-channel MOS transistors and two p-channel MOS transistors.
In general, two access transistors and two driver transistors are employed for an SRAM memory cell. For the CMOS memory cell, two load transistors are further employed as load elements in addition to these transistors.
A conventional CMOS memory cell is now described with reference to FIG. 19. Referring to FIG. 19, element forming regions 120a, 120b, 120c and 120d separated by a field isolation film 103 are formed on the surface of a silicon substrate. An access transistor T1 and a driver transistor T3 are formed on the element forming region 120a. 
An access transistor T2 and a driver transistor T4 are formed on the element forming region 120b. A load transistor T5 is formed on the element forming region 120c. A load transistor T6 is formed on the element forming region 120d. 
A gate electrode 104c is formed across the element forming regions 120a and 120b. A gate electrode 104a is formed across the element forming regions 120a and 120c. A gate electrode 104b is formed across the element forming regions 120b and 120d. Contact holes 112a, 112b and 112c are formed to expose the surface of the element forming region 120a. 
Contact holes 112d, 112e and 112f are formed to expose the surface of the element forming region 120b. Contact holes 112g and 112h are formed to expose the surface of the element forming region 120c. Contact holes 112i and 112j are formed to expose the surface of the element forming region 120d. 
Contact holes 112k and 112m are formed to expose the surface of an n well 102b. A gate electrode 104d belongs to another memory cell adjacent to this memory cell. A plurality of such memory cells are formed on a silicon substrate in a single SRAM.
An exemplary method of manufacturing the aforementioned memory cell is now described with reference to sectional views taken along the line XXxe2x80x94XX in FIG. 19. Referring to FIG. 20, a p well 102a is formed on a prescribed region of a silicon substrate 101. The gate electrodes 104a and 104d are formed on the surface of the p well 102a through a gate insulator film 105 with masks of on-gate insulator films 106a and 106b. 
An impurity such as phosphorus, for example, is injected through the gate electrodes 104a and 104d and the on-gate insulator films 106a and 106b serving as masks, thereby forming an nxe2x88x92drain region 109a and an nxe2x88x92source region 109b. 
Referring to FIG. 21, a silicon oxide film (not shown) is formed by CVD, for example, to cover the gate electrodes 104a and 104d and the on-gate insulator films 106a and 106b. The silicon oxide film is anisotropically etched thereby forming side wall insulator films 107a on both side surfaces of the gate electrode 104a. Further, side wall insulator films 107b are formed on both side surfaces of the gate electrode 104d. 
An n-type impurity is injected through the side wall insulator films 107a and 107b and the on-gate insulator films 106a and 106b serving as masks, thereby forming an n+drain region 110a and an n+source region 110b. 
Referring to FIG. 22, an interlayer insulator film 111 consisting of a silicon oxide film is formed on the silicon substrate 101 by CVD, to cover the side wall insulator films 107a and 107b and the on-gate insulator films 106a and 106b. A prescribed resist pattern (not shown) is formed on the interlayer insulator film 111.
The interlayer insulator film 111 is anisotropically etched through the resist pattern serving as a mask, thereby forming the contact hole 112b exposing the surface of the n+drain region 10a. Further, the contact hole 112c is formed to expose the surface of the n+source region 110b. 
Referring to FIG. 23, a barrier metal film 113 consisting of a titanium film and a titanium nitride film is formed by sputtering, for example, to cover the side surfaces and the bottom surfaces of the contact holes 112a and 112c and the upper surface of the interlayer insulator film 111. A tungsten film (not shown) is formed on the barrier metal film 113 by CVD, for example.
A resist pattern (not shown) is formed on the tungsten film. The tungsten film and the barrier metal film 113 are anisotropically etched through the resist pattern serving as a mask, thereby forming wiring layers 114a, 114b and 114c. A principal part of the memory cell of the SRAM is completed through the aforementioned steps.
In the aforementioned SRAM, however, six MOS transistors must be formed for each memory cell. As compared with another high-resistance memory cell, for example, employing no transistors as load elements, therefore, the area occupied by the memory cell is increased.
Further, the contact holes for electrical connection with the transistors must be provided for the respective transistors. Consequently, the size of the semiconductor chip may be disadvantageously increased.
When approximating the contact holes to the gate electrode or narrowing the element forming regions in order to solve these problems, however, the following problems arise:
When approximating the contact holes to the gate electrode, the surface of the gate electrode 104a may be exposed when the contact hole 112c is formed in the step shown in FIG. 22, for example. Therefore, tungsten embedded in the contact hole 112c may be shorted to the gate electrode 104a. 
When narrowing the element forming regions, the field isolation film 103 may be excessively etched when the contact hole 112b is formed in the step shown in FIG. 22, for example. Therefore, a current may leak from tungsten embedded in the contact hole 112b to the p well 102 through the excessively etched part of the field isolation film 103.
Therefore, the area occupied by the memory cell is so hard to narrow that the chip size cannot be reduced.
The present invention has been proposed in order to solve the aforementioned problems, and an object thereof is to provide a semiconductor device capable of performing desired operations and reducing the chip size.
A semiconductor device according to a first aspect of the present invention comprises a first conductivity type region, an element forming region, a semiconductor element, an insulator film and a first contact hole. The first conductivity type region is formed on the main surface of a semiconductor substrate. The element forming region is separated on the main surface of the semiconductor substrate by an element isolation film and formed on the surface of the first conductivity type region. The semiconductor element is formed on the element forming region. The insulator film is formed on the semiconductor substrate to cover the semiconductor element. The first contact hole is formed in the insulator film, to expose the surface of the element forming region. The semiconductor element has an electrode part, a pair of second conductivity type first impurity regions, and a second conductivity type second impurity region. The electrode part is formed across the element forming region. The pair of second conductivity type first impurity regions are formed on one side and another side of the element forming region through the electrode part respectively, and have a first impurity concentration. The second conductivity type second impurity region is formed on at least one of the first impurity regions to include a contact part of the first contact hole, and has a second impurity concentration higher than the first impurity concentration. An etching prevention film different in etching property from the insulator film is formed between the insulator film and the semiconductor element to cover the electrode part in direct contact with both side surfaces of the electrode part. The first contact hole is arranged to planarly overlap with the electrode part. The wording xe2x80x9cplanarly overlapxe2x80x9d means xe2x80x9coverlap with respect to the layout pattern of the semiconductor devicexe2x80x9d. This also applies to the following description.
Although the first contact hole is arranged on the position planarly overlapping with the electrode part according to this semiconductor device, the surface of the electrode part is not exposed by etching for forming the first contact hole but the surface of the element forming region is exposed in a self-aligned manner since the electrode part is covered with the etching prevention film coming into direct contact with the side surfaces. Therefore, the electrode part is not shorted to a wiling material embedded in the first contact hole. Consequently, a semiconductor device having a further reduced chip size and performing desired operations is obtained.
Preferably, the insulator film includes a silicon oxide film, and the etching prevention film includes at least a silicon nitride film.
In this case, the ratio (etching selection ratio) of the etching rate for the insulator film to the etching rate for the etching prevention film for forming the first contact hole can be increased so that the silicon oxide film can be etched without substantially etching the silicon nitride film.
More preferably, the etching prevention film further includes a silicon oxide film formed under the silicon nitride film.
In this case, the etching selection ratio can be more increased.
More preferably, the insulator film contains an impurity for improving the etching selection ratio with respect to the etching prevention film.
Also in this case, the etching selection ratio can be more increased.
Such an impurity is preferably prepared from phosphorus or boron.
Preferably, the semiconductor device further includes another electrode part formed across the element forming region at a space from the electrode part, the other electrode part is.covered with the etching prevention film coming into direct contact with at least the side surfaces, and the first contact hole is arranged to planarly overlap with the other electrode part.
In this case, the first contact hole is arranged to planarly overlap with the other electrode part, whereby the chip size of the semiconductor device having a plurality of electrode parts can be readily reduced.
It is preferable that the space between the electrode part and the other electrode part is longer than twice the thickness of the etching prevention film and the thickness of the etching prevention film is smaller than the height of the electrode part and the other electrode part.
In this case, the surface of the element forming region located between the electrode part and the other electrode part adjacent to each other can be reliably exposed in a self-aligned manner when forming the first contact hole.
Further, the second impurity region is preferably formed by introducing an impurity through a contact part of the first contact hole.
In this case, the second impurity region can be readily formed in a self-aligned manner through the contact part.
Preferably, the semiconductor device further comprise a second contact hole formed in the insulator film and arranged not to planarly overlap with the electrode part and a second conductivity type third impurity region including a contact part of the second contact hole, formed on another one of the first impurity regions and having a third impurity concentration higher than the first impurity concentration, the semiconductor element is a transistor including the third impurity region, and the distance between the third impurity region and a portion immediately under the side surface of the electrode part on the side where the third impurity region is located on the main surface of the semiconductor substrate is longer than the distance between the second impurity region and a portion immediately under the side surface of the electrode part on the side where the second impurity region is located on the main surface of the semiconductor substrate.
In this case, a transistor having the pair of first impurity regions, the second impurity region and the third impurity region can have a kind of parasitic resistance consisting of the first impurity regions between the third impurity region and the portion immediately under the side surface of the electrode part on the side where the third impurity region is located. Current drivability of the transistor having such parasitic resistance can be intentionally reduced.
The third impurity region is preferably formed by introducing an impurity through the contact part of the second contact hole.
In this case, the third impurity region can be readily formed in a self-aligned manner through the contact part.
Preferably, the element isolation film is covered with the etching prevention film, and the first or second contact hole is arranged to planarly overlap with the element isolation film.
In this case, the element forming region can be further narrowed for further reducing the chip size of the semiconductor device. The element isolation film, covered with the etching prevention film, is not excessively etched when forming each contact hole. The second or third impurity region is formed by introducing the impurity through the contact part of each contact hole, thereby suppressing current leakage from a portion close to the boundary between the element isolation film and the element forming region.
Preferably, the semiconductor device further comprises a third contact hole formed in the insulator film to planarly overlap with the electrode part and a second conductivity type fourth impurity region including a contact part of the third contact hole, formed on another one of the first impurity regions and having a second impurity concentration higher than the first impurity concentration, the semiconductor element is a transistor further including the fourth impurity region, and the distance between the fourth impurity region and a portion immediately under the side surface of the electrode part on the side where the fourth impurity region is located on the main surface of the semiconductor substrate is substantially identical to the distance between the second impurity region and a portion immediately under the side surface of the electrode part on the side where the second impurity region is located on the main surface of the semiconductor substrate.
In this case, a transistor having the electrode part, the pair of first impurity regions, the second impurity region and the fourth impurity region is reduced in dispersion of operations and stabilized in operation due to the aforementioned distance relation.
Preferably, the electrode length of the electrode part is larger in the portion where the first contact hole and the third contact hole overlap with the electrode part as compared with the remaining portion.
In this case, the first contact hole and the third contact hole located on both sides of the electrode part can be readily formed without substantially widening the element forming region.
Preferably, the first or third contact hole is arranged to planarly overlap with the element isolation film.
In this case, the element forming region can be further narrowed, for further reducing the chip size of the semiconductor device. Further, the element isolation film, covered with the etching prevention film, can be inhibited from excessive etching when forming the first and third contact holes, for suppressing a leakage current.
More preferably, the fourth impurity region is formed by introducing an impurity through the contact part of the third contact hole.
In this case, the fourth impurity region can be readily formed in a self-aligned manner through the contact part.
Preferably, the semiconductor device further comprises a second contact hole formed in the insulator film and arranged not to planarly overlap with the electrode part, a second conductivity type third impurity region including a contact part of the second contact hole, formed on another one of the first impurity regions and having a second impurity concentration higher than the first impurity concentration, a third contact hole formed in the insulator film and arranged to planarly overlap with the electrode part, and a second conductivity type fourth impurity region including a contact part of the third contact hole, formed on another one of the first impurity regions and having a second impurity concentration higher than the first impurity concentration. It is preferable that a plurality of semiconductor devices are formed on the semiconductor substrate, and the semiconductor element includes a first transistor having the electrode part, the pair of first impurity regions, the second impurity region and the third impurity region and a second transistor having the electrode part, the pair of first impurity regions, the second impurity region and the fourth impurity region. Further, the distance between the third impurity region and a portion immediately under the side surface of the electrode part on the side where the third impurity region is located on the main surface of the semiconductor substrate is longer than the distance between the second impurity region and a portion immediately under the side surface of the electrode part on the side where the second impurity region is located on the main surface of the semiconductor substrate, and the distance between the fourth impurity region and a portion immediately under the side surface of the electrode part on the side where the fourth impurity region is located on the main surface of the semiconductor substrate is substantially identical to the distance between the second impurity region and the portion immediately under the side surface of the electrode part on the side where the second impurity region is located on the main surface of the semiconductor substrate.
In this case, the first transistor has a parasitic resistance as described above, so that the operability (current drivability) thereof can be intentionally reduced. The second transistor, having no such parasitic resistance, is inhibited from dispersion of operations and stabilized in operation.
Preferably, the semiconductor device has a static memory cell including a pair of driver transistors having cross-connected gates and drains, a pair of access transistors having sources connected to the drains of the driver transistors respectively, and a pair of load transistors having drains connected to the drains of the driver transistors respectively and gates connected to the gates of the driver transistors respectively, the access transistors are the first transistor, and the driver transistors and the load transistors are the second transistor.
In this case, the access transistors of the static memory cell are formed by the first transistor in particular, whereby current drivability of the access transistors is intentionally reduced due to presence of parasitic resistance and the ratio (beta ratio) of the current drivability of the driver transistors to the current drivability of the access transistors is increased. Consequently, operations of the static memory cell can be stabilized.
Preferably, the semiconductor device further comprises a conductor part formed to fill up the first contact hole and a wiring layer formed on the insulator film and electrically connected with the conductor part, the wiring layer partially covers the upper surface of the conductor part, and a portion of the upper surface of the conductor part not covered with the wiring layer is on a position lower than the upper surface of the insulator film.
In this case, the substantial horizontal space between adjacent wiring layers can be reduced for further reducing the size of a wire forming region as well as the chip size of the semiconductor device.
The semiconductor device preferably further comprises a fourth contact hole formed in the insulator film and the element isolation film for exposing the surface of the first conductivity type region.
In this case, the fourth contact hole for stabilizing the potential of the first conductivity type region can be readily formed with no restriction by the layout pattern.
A semiconductor device according to another aspect of the present invention comprises an insulator film, a contact hole, a conductor part and a wiring layer. The insulator film is formed on the main surface of a semiconductor substrate. The contact hole is formed in the insulator film for exposing the main surface of the semiconductor substrate. The conductor part is embedded in the contact hole. The wiring layer is formed on the insulator film and electrically connected with the conductor part. The wiring layer partially covers the upper surface of the conductor part, and a portion of the upper surface of the conductor part not covered with the wiring layer is on a position lower than the upper surface of the insulator film.
According to this semiconductor device, the portion of the upper surface of the conductor part not covered with the wiling layer is on the position lower than the upper surface of the insulator film, whereby the substantial horizontal distance between the wiring layer connected to the conductor part and another wiring layer can be reduced. Thus, the size of the region for forming the wiring layer as well as the chip size of the semiconductor device can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.